`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:56:35 04/20/2011 
// Design Name: 
// Module Name:    PC 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module PC(clk, muxToPC, PCWrite, PC);

	input clk;
	input [15:0] muxToPC;
	input PCWrite;
	output [15:0] PC;
	
	reg [15:0] PC;
	
	always @ (posedge clk)
	begin
		if (PCWrite)
			PC <= muxToPC;
	end


endmodule
